SSC I/O Ports

Used to create an I/O Port configuration, by unifying one of the SSC_MRST_P* with a SSC_MTSR_P* and a SSC_SCLK_P* ports. More...

Macros
#define	SSC_MRST_P05   1
	Master mode RX, slave mode TX port P0.5. More...
#define	SSC_MRST_P14   0
	Master mode RX, slave mode TX port P1.4. More...
#define	SSC_MRST_P15   2
	Master mode RX, slave mode TX port P1.5. More...
#define	SSC_MTSR_P04   (1 << 2)
	Master mode TX, slave mode RX port P0.4. More...
#define	SSC_MTSR_P13   (0 << 2)
	Master mode TX, slave mode RX port P1.3. More...
#define	SSC_MTSR_P14   (2 << 2)
	Master mode TX, slave mode RX port P1.4. More...
#define	SSC_SCLK_P03   (1 << 4)
	Synchronous clock port P0.3. More...
#define	SSC_SCLK_P12   (0 << 4)
	Synchronous clock port P1.2. More...
#define	SSC_SCLK_P13   (2 << 4)
	Synchronous clock port P1.3. More...

Detailed Description

Used to create an I/O Port configuration, by unifying one of the SSC_MRST_P* with a SSC_MTSR_P* and a SSC_SCLK_P* ports.

E.g.:

SSC_MRST_P05 | SSC_MTSR_P4 | SSC_SCLK_P03.

The ports have the following functions:

Type	Master Mode	Slave Mode
MRST	RX port	TX port
MTSR	TX port	RX port
SCLK	TX clock	RX clock

Macro Definition Documentation

#define SSC_MRST_P05   1

Master mode RX, slave mode TX port P0.5.

#define SSC_MRST_P14   0

Master mode RX, slave mode TX port P1.4.

#define SSC_MRST_P15   2

Master mode RX, slave mode TX port P1.5.

#define SSC_MTSR_P04   (1 << 2)

Master mode TX, slave mode RX port P0.4.

#define SSC_MTSR_P13   (0 << 2)

Master mode TX, slave mode RX port P1.3.

#define SSC_MTSR_P14   (2 << 2)

Master mode TX, slave mode RX port P1.4.

#define SSC_SCLK_P03   (1 << 4)

Synchronous clock port P0.3.

#define SSC_SCLK_P12   (0 << 4)

Synchronous clock port P1.2.

#define SSC_SCLK_P13   (2 << 4)

Synchronous clock port P1.3.